In modern electronics industry, many digital hardware designs are described in a hardware description language. For example, the IEEE standard 1364-1995 hardware description language defined in “IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language,” published in 1996 by IEEE, is one of the popular hardware description languages. A digital hardware design written in such a hardware description language has to be verified for its intended functionality before it is compiled to generate the final netlist for manufacturing. This design verification task has long been associated with logic simulation.
A hardware-assisted design verification system uses a hardware accelerator to enhance the performance of logic simulation for a class of design verification tasks that require higher performance than a software-based verification system can provide. The hardware accelerator is a specialized logic simulation machine consisting of a large number of logic processors, each capable of simulating a logic gate. For example, the U.S. Pat. No. 4,306,286 “Logic Simulation Machine” issued Dec. 15, 1981 to Cocke et al. discloses such a logic simulation machine. It is noted that it is possible to perform verification without using such a hardware accelerator.
One type of hardware device useful as a hardware accelerator is the Cobalt™ product from Quickturn Design Systems, Inc., San Jose, Calif. (the assignee of the present invention). In a typical hardware-assisted design verification system, the hardware accelerator is connected to a host workstation, which runs a verification control program to load the compiled design under verification (also referred to herein as “DUV” or “user design”) into the hardware accelerator, initiate logic simulation, terminate logic simulation, and unload the simulation results from the hardware accelerator. The user checks the simulation results against the expected results to see if the DUV has been simulated as expected. At the early stage of design verification, it is relatively easy for the user to find the problems in the DUV when the user finds the simulation results incorrect. It is, however, getting more difficult to debug the DUV at later design verification stages. Because of this problem, the user often wants to check the intermediate values of some key signals in the DUV during logic simulation. In order to satisfy such a requirement from the user, the design verification system provides support for signal visibility operations to make the signals in the DUV visible or accessible to the user during logic simulation.
It is easy for a software-based verification system to provide such support for signal visibility operations, but not very easy for a hardware-assisted verification system, since it requires extra communications between the host workstation and the hardware accelerator simulating the DUV.
Initial loading of the DUV into the hardware accelerator is usually done through a very general I/O interface like the SCSI interface. It is possible to use this I/O interface to access a small number of signals in the DUV during logic simulation. In that case, the interface control program in the hardware accelerator first identifies the requested signals, locates them, reads their values, and sends them back to the host workstation.
Signal visibility operations usually include not only operations to examine the intermediate value of a particular signal but also operations to deposit a logic value on the signal for subsequent simulation steps. Using these basic operations, the user can examine the value of a register or deposit a value on the register by accessing a group of signals corresponding to the register bits. By accessing a group of related registers, the user also can write data to or read data from a memory.
In order to take advantage of the advanced semiconductor chip technologies, an increasing number of DUVs include memories of large capacity. With the conventional signal visibility operations, it takes a long time to load data to or unload data from the large-capacity memories in the DUV, because the basic signal visibility operations are based on the low-level examine or deposit operations on individual signals.
To accelerate the loading and unloading operations for registers and memories in the DUV, a hardware-assisted design verification system can use a special communication channel between the host workstation and the hardware accelerator, dedicated for signal visibility operations. To minimize the overhead in accessing the requested signals in the DUV simulated on the hardware accelerator, the special communication channel is directly connected to the input and output data buffers, which in turn directly interfaces to the DUV without any interface control program.
One of the interface schemes with data buffering is disclosed in the U.S. Pat. No. 5,721,953 “Interface for Logic Simulation Using Parallel Bus for Concurrent Transfers and Having FIFO Buffers for Sending Data to Receiving Units When Ready” issued Feb. 24, 1998 to Fogg, Jr. et al., which discusses about the interface with a First-In-First-Out or FIFO buffer provided between the host computer and the logic simulation machine to minimize the interface delays. The disclosure of U.S. Pat. No. 5,721,953 is incorporated herein by reference in its entirety.
The output signals are assigned to the bits of the output data buffer, while the input signals are assigned to the bits of the input data buffer. For an examine operation (i.e., observing or reading the value of a signal), the verification control program initiates a data transfer to send the signal values stored in the output data buffer to the host workstation and selects the values of the requested signals. For a deposit operation (i.e., writing the value of a signal), the verification control program assembles the values to deposit and initiates a data transfer to send them to the input data buffer in the hardware accelerator. Additional wiring and logic components required for interfacing to the DUV are synthesized when the DUV is compiled for logic simulation.
The wiring and logic components synthesized for signal visibility operations are not part of the DUV, but virtual components merged with the DUV for logic simulation. Virtual logic components are often used for a testbench that generates inputs to the DUV and checks the simulation outputs, as described in a technical paper “The IBM Engineering Verification Engine” published by Beece et al. in the Proceedings of the 25th ACM/IEEE Design Automation Conference, June 1988, pages 218–224.
The static assignment of the input and output signals to the bits of the input and output data buffers is acceptable if the number of visible signals for signal visibility operations is relatively small. It is, however, not desirable for a large number of visible signals, because there is a limitation on the number of physically available data buffer bits.
One of the solutions to the problem of accessibility to signals within the DUV is to time-multiplex two or more signals for each bit in the data buffer to effectively increase the number of visible signals. One method of time-multiplexing multiple signals is disclosed in the U.S. Pat. No. 5,596,742, entitled “Virtual Interconnections for Reconfigurable Logic Systems” issued Jan. 21, 1997 to Agarwal et al., which discusses a compilation technique to intelligently multiplex each physical wire among multiple logical wires and pipelining these connections. Another time multiplexing method, which differs significantly from that disclosed in Agarwal, is disclosed in U.S. Pat. No. 5,960,191, entitled “Emulation System with Time-Multiplexed Interconnect” issued Sep. 28, 1999 to Sample et al., which discloses a hardware emulation system that time-multiplexes multiple design signals onto physical logic chip pins and printed circuit board. Another disclosure relating to time-multiplexing is disclosed in U.S. Pat. No. 6,020,760, entitled “I/O Buffer Circuit with Pin Multiplexing” issued Feb. 1, 2000 to Sample et al, which discloses an integrated circuit for implementing reconfigurable logic with an input/output buffer circuit time-multiplexing at least two signals onto an input/output pin to increase the effective I/O pin availability. U.S. Pat. Nos. 5,596,742, 5,960,191 and 6,020,760 are incorporated herein by reference in their entirety.
Although these time-multiplexing methods can effectively increase the number of visible signals through the data buffers, they do not address the performance issue in accessing the registers and memories in the DUV. Grouping of the signals required to access a register or memory can reduce the overhead incurred by gathering and scattering the bit values for the signals in a group. This signal grouping method may, however, impose severe restrictions on time-multiplexing multiple signals, because all the signals in a group have to be visible at the same time, and there may be many such signal groups, and there may be some signals shared by two or more groups.
With or without signal grouping, several steps are required to access one register using the low-level examine and deposit operations; more steps are required to access one memory word. Therefore, it is expected to take a very long time for the verification control program to load/unload a large number of data to/from a memory. Such time-consuming loading and unloading operations effectively degrade the overall simulation performance render the simulation much less effective, as fewer clock cycles will be simulated.
If a DUV contains many large-capacity memories, this performance degradation will become very serious, effectively nullifying the enhancement of simulation performance with the hardware accelerator. It would be desirable to provide a method and apparatus for reducing the time required for data loading and unloading. It would also be desirable to provide a method and apparatus for easier access to the registers and memories.